View PXAS30KFA_513285.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
XA-S3 XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
Preliminary specification Supersedes data of 2000 Aug 22 2000 Dec 01
Philips Semiconductors
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
GENERAL DESCRIPTION
The XA-S3 device is a member of Philips Semiconductors' XA (eXtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-S3 device combines many powerful peripherals on one chip. With its high performance A/D converter, timers/counters, watchdog, Programmable Counter Array (PCA), I2C interface, dual UARTs, and multiple general purpose I/O ports, it is suited for general multipurpose high performance embedded control functions.
* Three standard counter/timers with enhanced features. All timers
have a toggle output capability.
* Watchdog timer. * 5-channel 16-bit Programmable Counter Array (PCA). * I2C-bus serial I/O port with byte-oriented master and slave
functions.
Specific features of the XA-S3
* 2.7 V to 5.5 V operation. * 32 K bytes of on-chip EPROM/ROM program memory. * 1024 bytes of on-chip data RAM. * Supports off-chip addressing up to 16 megabytes (24 address
lines). A clock output reference is added to simplify external bus interfacing.
* Two enhanced UARTs with independent baud rates. * Seven software interrupts. * Active low reset output pin indicates all reset occurrences
(external reset, watchdog reset and the RESET instruction). A reset source register allows program determination of the cause of the most recent reset.
* High performance 8-channel 8-bit A/D converter with automatic
channel scan and repeated read functions. Completes a conversion in 4.46 microseconds at 30 MHz. Alternate operating mode allows 10-bit conversion results.
* 50 I/O pins, each with 4 programmable output configurations. * 30 MHz operating frequency at 2.7-5.5 V VDD. * Power saving operating modes: Idle and Power-down. Wake-up
from power-down via an external interrupt is supported.
* 68-pin PLCC and 80-pin PQFP packages.
ORDERING INFORMATION
ROMless PXAS30KBA PXAS30KBBE PXAS30KFA PXAS30KFBE ROM PXAS33KBA PXAS33KBBE PXAS33KFA PXAS33KFBE EPROM PXAS37KBA PXAS37KBBE PXAS37KFA PXAS37KFBE OTP OTP OTP OTP TEMPERATURE RANGE (C) AND PACKAGE 0 to +70, Commercial 68-pin Plastic Leaded Chip Carrier 0 to +70, Commercial 80-pin Plastic Low Profile Quad Flat Pack -40C to +85C, Industrial 68-pin Plastic Leaded Chip Carrier -40C to +85C, Industrial 80-pin Plastic Low Profile Quad Flat Pack FREQ. (MHz) 30 30 30 30 DRAWING NUMBER SOT188-3 SOT315-1 SOT188-3 SOT315-1
2000 Dec 01
2
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
PIN CONFIGURATIONS 68-pin PLCC package
P2.7/A19D15 P2.6/A18D14 P2.5/A17D13 P2.4/A16D12 P2.2/A14D10 61 60 P2.1/A13D9 59 P2.0/A12D8 58 P0.7/A11D7 57 P0.6/A10D6 56 P0.5/A9D5 55 VSS 54 VDD 53 P0.4/A8D4 52 P0.3/A7D3 51 P0.2/A6D2 50 RST 49 CLKOUT 48 PSEN 47 ALE/PROG 46 P0.1/A5D1 45 P0.0/A4D0 44 P6.1/A23 27 P5.4/AD4 28 P5.5/AD5 29 P5.6/AD6/SCL 30 P5.7/AD7/SDA 31 AVREF- 32 AVREF+ 33 AVDD 34 AVSS 35 P1.0/A0/WRH 36 P1.1/A1 37 P1.2/A2 38 P1.3/A3 39 P1.4/RxD1 40 P1.5/TxD1 41 P1.6/T2 42 P1.7/T2EX 43 P6.0/A22 P2.3/A15D11 62 P4.5/CEX4 P4.4/CEX3 P4.3/CEX2 P4.2/CEX1 P4.1/CEX0 P4.6/A20 P4.0/ECI
XTAL1 68
9 P4.7/A21 10 P3.0/RxD0 11
8
7
6
5
4
3
2
1
67
XTAL2
V DD
V SS
66
65
64
63
P3.1/TxD0 12 P3.2/INT0 13 P3.3/INT1 14 P3.4/T0 15 P3.5/T1/BUSW 16 P3.6/WRL 17 P3.7/RD 18 RSTOUT 19 VSS 20 VDD 21 EA/WAIT/VPP 22 P5.0/AD0 23 P5.1/AD1 24 P5.2/AD2 25 P5.3/AD3 26
PLASTIC LEADED CHIP CARRIER
SU00936
2000 Dec 01
3
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
80-pin LQFP package
P2.7/A19D15 P2.6/A18D14 P2.5/A17D13 P2.4/A16D12 P2.2/A14D10 61 60 NC 59 P2.1/A13D9 58 P2.0/A12D8 57 P0.7/A11D7 56 P0.6/A10D6 55 P0.5/A9D5 54 VSS 53 VSS 52 VDD 51 VDD 50 P0.4/A8D4 49 P0.3/A7D3 48 P0.2/A6D2 47 RST 46 CLKOUT 45 PSEN 44 ALE/PROG 43 P0.1/A5D1 42 P0.0/A4D0 41 P6.1/A23 21 NC 22 P5.4/AD4 23 P5.5/AD5 24 P5.6/AD6/SCL 25 P5.7/AD7/SDA 26 AVREF- 27 AVREF+ 28 AV DD 29 AV DD 30 AVSS 31 AVSS 32 P1.0/A0/WRH 33 P1.1/A1 34 P1.2/A2 35 P1.3/A3 36 P1.4/RxD1 37 P1.5/TxD1 38 P1.6/T2 39 P1.7/T2EX 40 P6.0/A22 P2.3/A15D11 62 P4.5/CEX4 P4.4/CEX3 P4.3/CEX2 P4.2/CEX1 P4.1/CEX0
P4.6/A20
P4.0/ECI
XTAL1 68
80 NC P4.7/A21 P3.0/RxD0 P3.1/TxD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/BUSW P3.6/WRL 1 2 3 4 5 6 7 8 9
79
78
77
76
75
74
73
72
71
70
69
67
XTAL2
V DD
V DD
V SS
V SS
NC
66
65
64
63
P3.7/RD 10
LOW PROFILE PLASTIC QUAD FLAT PACK
RSTOUT 11 VSS 12 VSS 13 VDD 14 VDD 15 EA/WAIT/VPP 16 P5.0/AD0 17 P5.1/AD1 18 P5.2/AD2 19 P5.3/AD3 20
SU00937
2000 Dec 01
4
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
LOGIC SYMBOL
VDD VSS
XTAL1 ECI CEX0 CEX1 PORT4 XTAL2 CEX2 CEX3 CEX4 A20 AVDD AVREF+ AVREF- AVSS PORT5 A21
CLKOUT ALE PSEN RSTOUT RST EA/WAIT
A/D INPUTS SCL SDA
PORT6
A22 A23
WRH/A0 A1 A2 PORT1 A3 RxD1 TxD1 T2 T2EX RxD0 TxD0 INT0 PORT3 INT1 T0 T1/BUSW WRL RD PORT2 PORT0
ADDRESS AND DATA BUS
SU00847A
2000 Dec 01
5
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
BLOCK DIAGRAM
XA CPU Core
Program Memory Bus 32K Bytes ROM/EPROM Data Bus UART 1
SFR bus UART 0
1024 Bytes Static RAM
I2C Port 0 Timer 0, 1 Port 1 Timer 2 Port 2 Watchdog Timer
Port 3
Port 4
PCA
Port 5 Port 6
Input Port/ A/D
SU00846
2000 Dec 01
6
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC PLCC VSS 1, 20, 55 LQFP 12, 13, 53, 54, 69, 70 14, 15, 51, 52, 71, 72 47 I Ground: 0 V reference. TYPE NAME AND FUNCTION
VDD
2, 21, 54
I
Power Supply: This is the power supply voltage for normal, idle, and power down operation. Reset: A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at the address contained in the reset vector. Reset Output: This pin outputs a low whenever the XA-S3 processor is reset for any reason. This includes an external reset via the RST pin, watchdog reset, and the RESET instruction. Address Latch Enable/Program Pulse: A high output on the ALE pin signals external circuitry to latch the address portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order to process a bus cycle. Program Store Enable: The read strobe for external program memory. When the microcontroller accesses external program memory, PSEN is driven low in order to enable memory devices. PSEN is only active when external code accesses are performed. External Access/Bus Wait: The EA input determines whether the internal program memory of the microcontroller is used for code execution. The value on the EA pin is latched as the external reset input is released and applies during later execution. When latched as a 0, external program memory is used exclusively. When latched as a 1, internal program memory will be used up to its limit, and external program memory used above that point. After reset is released, this pin takes on the function of bus WAIT input. If WAIT is asserted high during an external bus access, that cycle will be extended until WAIT is released. Crystal 1: Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits. Crystal 2: Output from the oscillator amplifier. Clock Output: This pin outputs a buffered version of the internal CPU clock. The clock output may be used in conjunction with the external bus to synchronize WAIT state generators, etc. The clock output may be disabled by software. Analog Power Supply: Positive power supply input for the A/D converter. Analog Ground. A/D Positive Reference Voltage: High end reference for the A/D converter. A/D Negative Reference Voltage: Low end reference for the A/D converter. Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction byte and address lines 4 through 11.
RST
50
I
RSTOUT
19
11
O
ALE/PROG
47
44
I/O
PSEN
48
45
O
EA/WAIT/VPP
22
16
I
XTAL1 XTAL2 CLKOUT
68 67 49
68 67 46
I I O
AVDD AVSS AVREF+ AVREF- P0.0 - P0.7
33 34 32 31 45, 46, 51-53, 56-58
28, 29 30, 31 27 26 42, 43, 48-50, 55-57
I I I I I/O
2000 Dec 01
7
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
PIN NUMBER MNEMONIC PLCC P1.0 - P1.7 35-42 LQFP 32-39 I/O Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 1 also provides various special functions as described below: A0/WRH (P1.0) Address bit 0 of the external address bus when the eternal data bus is configured for an 8-bit width. When the external data bus is configured for a 16-bit width, this pin becomes the high byte write strobe. A1 (P1.1): Address bit 1 of the external address bus. A2 (P1.2): Address bit 2 of the external address bus. A3 (P1.3): Address bit 3 of the external address bus. RxD1 (P1.4): Serial port 1 receiver input. TxD1 (P1.5): Serial port 1 transmitter output. T2 (P1.6): Timer/counter 2 external count input or overflow output. T2EX (P1.7): Timer/counter 2 reload/capture/direction control. Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high data/instruction byte and address lines 12 through 19. When the external data/address bus is used in 8-bit mode, the number of address lines that appear on Port 2 is user programmable in groups of 4 bits. P3.0 - P3.7 11-18 3-10 I/O Port 3: Port 3 is an 8-bit I/O port with a user-configurable output type. Port 3 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 3 also provides the various special functions as described below: RxD0 (P3.0): Receiver input for serial port 0. TxD0 (P3.1): Transmitter output for serial port 0. INT0 (P3.2): External interrupt 0 input. INT1 (P3.3): External interrupt 1 input. T0 (P3.4): Timer/counter 0 external count input or overflow output. T1 / BUSW (P3.5): Timer/counter 1 external count input or overflow output. The value on this pin is latched as an external chip reset is completed and defines the default external data bus width. WRL (P3.6): External data memory low byte write strobe. RD (P3.7): External data memory read strobe. Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. Port 4 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 4 also provides various special functions as described below: ECI (P4.0): PCA External clock input. CEX0 (P4.1): Capture/compare external I/O for PCA module 0. CEX1 (P4.2): Capture/compare external I/O for PCA module 1. CEX2 (P4.3): Capture/compare external I/O for PCA module 2. CEX3 (P4.4): Capture/compare external I/O for PCA module 3. CEX4 (P4.5): Capture/compare external I/O for PCA module 4. A20 (P4.6): Address bit 20 of the external address bus. A21 (P4.7): Address bit 21 of the external address bus. TYPE NAME AND FUNCTION
35
32
O
36 37 38 39 40 41 42 P2.0 - P2.7 59-66
33 34 35 36 37 38 39 58, 59, 61-66
O O O I O I/O O I/O
11 12 13 14 15 16
3 4 5 6 7 8
I O I I I/O I/O
17 18 P4.0 - P4.7 3-10
9 10 73-79, 2
O O I/O
3 4 5 6 7 8 9 10
73 74 75 76 77 78 79 2
I I/O I/O I/O I/O I/O O O
2000 Dec 01
8
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
PIN NUMBER MNEMONIC PLCC P5.0 - P5.7 23-30 LQFP 17-20, 22-25 I/O Port 5: Port 5 is an 8-bit I/O port with a user-configurable output type. Port 5 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 5 also provides various special functions as described below. Port 5 pins used as A/D inputs must be configured by the user to the high impedance mode. 23 24 25 26 27 28 29 30 P6.0 - P6.7 43, 44 17 18 19 20 22 23 24 25 40, 41 I I I I I I I/O I/O I/O AD0 (P5.0): AD1 (P5.1): AD2 (P5.2): AD3 (P5.3): AD4 (P5.4): AD5 (P5.5): AD6/SCL (P5.6): AD7/SDA (P5.7): A/D channel 0 input. A/D channel 1 input. A/D channel 2 input. A/D channel 3 input. A/D channel 4 input. A/D channel 5 input. A/D channel 6 input. I2C serial clock input/output. A/D channel 7 input. I2C serial data input/output. TYPE NAME AND FUNCTION
Port 6: Port 6 is a 2-bit I/O port with a user-configurable output type. Port 6 latches have 1s written to them and are configured in the quasi-bidirectional mode during reset. The operation of Port 6 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section on I/O port configuration and the DC Electrical Characteristics for details. Port 6 also provides special functions as described below: A22 (P6.0): Address bit 22 of the external address bus. A23 (P6.1): Address bit 23 of the external address bus.
43 44
40 41
O O
Table 1. Special Function Registers
NAME DESCRIPTION
SFR Address
BIT FUNCTIONS AND ADDRESSES MSB 3F7 3F6 - 3FE
ADCS6
LSB 3F5 - 3FD
ADCS5
Reset Value 00h 00h 0Fh xx xx xx xx xx xx xx xx xx
3F4 - 3FC
ADCS4
3F3
ADRES
3F2
ADMOD
3F1
ADSST
3F0
ADINT
ADCON#* A/D control register ADCS#* ADCFG# ADRSH0# ADRSH1# ADRSH2# ADRSH3# ADRSH4# ADRSH5# ADRSH6# ADRSH7# ADRSL# BCR# BTRH BTRL CCON#* CMOD# CH# CL# CCAPM0# CCAPM1# A/D channel select register A/D timing configuration A/D high byte result, channel 0 A/D high byte result, channel 1 A/D high byte result, channel 2 A/D high byte result, channel 3 A/D high byte result, channel 4 A/D high byte result, channel 5 A/D high byte result, channel 6 A/D high byte result, channel 7 Two LSBs of 10-bit A/D result Bus configuration register Bus timing register high byte Bus timing register low byte PCA counter control PCA mode control PCA counter high byte PCA counter low byte PCA module 0 mode PCA module 1 mode
43E 43F 4B9 4B0 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8 46A 469 468 41A 490 48B 48A 491 492
- 3FF
ADCS7
3FB
ADCS3
3FA
ADCS2
3F9
ADCS1
3F8
ADCS0
-
-
-
-
A/D Timing Configuration
- DW1 WM1 2D7 CF CIDL
- DW0 WM0 2D6 CR WDTE
CLKD DWA1 ALEW 2D5 - -
WAITD DWA0 - 2D4 CCF4 -
BUSD DR1 CR1 2D3 CCF3 -
BC2 DR0 CR0 2D2 CCF2 CPS1
BC1 DRA1 CRA1 2D1 CCF1 CPS0
BC0 DRA0 CRA0 2D0 CCF0 ECF
Note 1 FFh EFh 00h 00h 00h 00h
- -
ECOM0 ECOM1
CAPP0 CAPP1
CAPN0 CAPN1
MAT0 MAT1
TOG0 TOG1
PWM0 PWM1
ECCF0 ECCF1
00h 00h
2000 Dec 01
9
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
NAME CCAPM2# CCAPM3# CCAPM4# CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# CS DS ES I2CON#* I2STAT# I2DAT# I2ADDR# IEH* IEL#* IELB#* IPA0 IPA1 IPA2# IPA3# IPA4 IPA5 IPB0# IPB1# IPB2# P0* P1* P2* P3* P4#*
DESCRIPTION PCA module 2 mode PCA module 3 mode PCA module 4 mode PCA module 0 capture high byte PCA module 1 capture high byte PCA module 2 capture high byte PCA module 3 capture high byte PCA module 4 capture high byte PCA module 0 capture low byte PCA module 1 capture low byte PCA module 2 capture low byte PCA module 3 capture low byte PCA module 4 capture low byte Code segment Data segment Extra segment I2C control register I2C status register I2C data register I2C address register Interrupt enable high byte Interrupt enable low byte Interrupt enable B low byte Interrupt priority A0 Interrupt priority A1 Interrupt priority A2 Interrupt priority A3 Interrupt priority A4 Interrupt priority A5 Interrupt priority B0 Interrupt priority B1 Interrupt priority B2 Port 0 Port 1 Port 2 Port 3 Port 4
SFR Address
BIT FUNCTIONS AND ADDRESSES MSB - - - ECOM2 ECOM3 ECOM4 CAPP2 CAPP3 CAPP4 CAPN2 CAPN3 CAPN4 MAT2 MAT3 MAT4 TOG2 TOG3 TOG4 PWM2 PWM3 PWM4 LSB ECCF2 ECCF3 ECCF4
Reset Value 00h 00h 00h xx xx xx xx xx xx xx xx xx xx 00h 00h 00h
493 494 495 497 499 49B 49D 49F 496 498 49A 49C 49E 443 441 442
367 42C 46C 46D 46E 33F 427 426 42E 4A0 4A1 4A2 4A3 4A4 4A5 4A8 4A9 4AA 430 431 432 433 434 - 337 EA 377 - - - - - - - - - - 387 A11D7 38F T2EX 397
A19D15
366 ENA
365 STA
364 STO
363 SI
362 AA 0
361 CR1 0
360 CR0 0 GC 00h F8h xx 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 380 A4D0 388
A0/WRH
CR2
I2C Status Code/Vector I2C Slave Address 33E - 336 EAD 376 - 33D - 335 EPC 375 EI2 PT0 PT1 PPC - PTI0 PTI1 PC1 PC3 PI2 386 A10D6 38E T2 396
A18D14
33C - 334 ET2 374 EC4
33B ETI1 333 ET1 373 EC3 - - - - - - - - -
33A ERI1 332 EX1 372 EC2
339 ETI0 331 ET0 371 EC1 PX0 PX1 PT2 PAD PRI0 PRI1 PC0 PC2 PC4
338 ERI0 330 EX0 370 EC0
385 A9D5 38D TxD1 395
A17D13
384 A8D4 38C RxD1 394
A16D12
383 A7D3 38B A3 393
A15D11
382 A6D2 38A A2 392
A14D10
381 A5D1 389 A1 391
A13D9
FFh FFh FFh FFh FFh
390
A12D8
39F RD 3A7 A21
39E WRL 3A6 A20
39D T1 3A5 CEX4
39C T0 3A4 CEX3
39B INT1 3A3 CEX2
39A INT0 3A2 CEX1
399 TxD0 3A1 CEX0
398 RxD0 3A0 ECI
2000 Dec 01
10
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
NAME
DESCRIPTION
SFR Address
BIT FUNCTIONS AND ADDRESSES MSB 3AF 3AE
AD6/SCL
LSB 3AD AD5 - 3AC AD4 - 3AB AD3 - 3AA AD2 - 3A9 AD1 3B1 A23 3A8 AD0 3B0 A22
Reset Value
P5#* P6#* P0CFGA P1CFGA P2CFGA P3CFGA
Port 5 Port 6 Port 0 configuration A Port 1 configuration A Port 2 configuration A Port 3 configuration A
435 436 470 471 472 473 474 475 476 4F0 4F1 4F2 4F3 4F4 4F5 4F6 404 401 400 402 463 455 457 454 456
AD7/SDA
FFh FFh Note 5 Note 5 Note 5 Note 5 Note 5 Note 5
-
-
P4CFGA# Port 4 configuration A P5CFGA# Port 5 configuration A P6CFGA# Port 6 configuration A P0CFGB P1CFGB P2CFGB P3CFGB Port 0 configuration B Port 1 configuration B Port 2 configuration B Port 3 configuration B
-
-
-
-
-
-
Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5
P4CFGB# Port 4 configuration B P5CFGB# Port 5 configuration B P6CFGB# Port 6 configuration B PCON* PSWH* PSWL* PSW51* Power control register Program status word (high byte) Program status word (low byte) 80C51 compatible PSW
- 227 - 20F SM 207 C 217 C -
- 226 - 20E TM 206 AC 216 AC -
- 225 - 20D RS1 205 - 215 F0 -
- 224 - 20C RS0 204 - 214 RS1 -
- 223 - 20B IM3 203 - 213 RS0 -
- 222 - 20A IM2 202 V 212 V R_WD 221 PD 209 IM1 201 N 211 F1
R_CMD
Note 5 220 IDL 208 IM0 200 Z 210 P R_EXT Note 3 Note 7 00h 00h 00h 00h Note 2 Note 2 00h
RSTSRC# Reset source register RTH0 RTH1 RTL0 RTL1 S0CON* S0STAT#* S0BUF S0ADDR S0ADEN S1CON* S1STAT#* S1BUF S1ADDR Timer 0 reload register, high byte Timer 1 reload register, high byte Timer 0 reload register, low byte Timer 1 reload register, low byte Serial port 0 control register Serial port 0 extended status Serial port 0 data buffer register Serial port 0 address register Serial port 0 address enable Serial port 1 control register Serial port 1 extended status Serial port 1 data buffer register Serial port 1 address register
307 420 421 460 461 462 327 424 425 464 465 SM0_1 32F - SM0_0 30F -
306 SM1_0 30E -
305 SM2_0 30D -
304 REN_0 30C ERR0
303 TB8_0 30B FE0
302 RB8_0 30A BR0
301 TI_0 309 OE0
300 RI_0 308
STINT0
00h 00h xx 00h 00h
326 SM1_1 32E -
325 SM2_1 32D -
324 REN_1 32C ERR1
323 TB8_1 32B FE1
322 RB8_1 32A BR1
321 TI_1 329 OE1
320 RI_1 328
STINT1
00H 00h xx 00h
2000 Dec 01
11
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
NAME S1ADEN SCR SSEL* SWE SWR* T2CON* T2MOD* TH2 TL2 T2CAPH T2CAPL TCON* TH0 TH1 TL0 TL1 TMOD TSTAT* WDCON* WDL WFEED1 WFEED2
DESCRIPTION Serial port 1 address enable System configuration register Segment selection register Software interrupt enable Software interrupt request Timer 2 control register Timer 2 mode control Timer 2 high byte Timer 2 low byte Timer 2 capture, high byte Timer 2 capture, low byte Timer 0 and 1 control register Timer 0 high byte Timer 1 high byte Timer 0 low byte Timer 1 low byte Timer 0 and 1 mode control Timer 0 and 1 extended status Watchdog control register Watchdog timer reload Watchdog feed 1 Watchdog feed 2
SFR Address
BIT FUNCTIONS AND ADDRESSES MSB LSB
Reset Value 00h
466 440 403 47A 42A 418 419 459 458 45B 45A 287 410 451 453 450 452 45C 411 41F 45F 45D 45E GATE 28F - 2FF PEW2 C/T 28E - 2FE PRE1 M1 28D - 2FD PRE0 M0 28C - 2FC - GATE 28B - 2FB - C/T 28A T1OE 2FA
WDRUN
- 21F
ESWEN
- 21E
R6SEG
- 21D
R5SEG
- 21C
R4SEG
PT1 21B
R3SEG
PT0 21A
R2SEG
CM 219
R1SEG
PZ 218
R0SEG
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
- 357 - 2C7 TF2 2CF -
SWE7 356 SWR7 2C6 EXF2 2CE -
SWE6 355 SWR6 2C5 RCLK0 2CD RCLK1
SWE5 354 SWR5 2C4 TCLK0 2CC TCLK1
SWE4 353 SWR4 2C3
EXEN2
SWE3 352 SWR3 2C2 TR2 2CA -
SWE2 351 SWR2 2C1 C/T2 2C9 T2OE
SWE1 350 SWR1 2C0
CP/RL2
2CB -
2C8 DCEN
286 TR1
285 TF0
284 TR0
283 IE1
282 IT1
281 IE0
280 IT0 00h 00h 00h 00h 00h
TF1
M1 289 - 2F9
WDTOF
M0 288 T0OE 2F8 -
00h 00h Note 6 00h xx xx
NOTES: * SFRs are bit addressable. # SFRs are modified from or added to XA-G3 SFRs. 1. At reset, the BCR is loaded with the binary value 00000a11, where "a' is the value on the BUSW pin. This defaults the address bus size to 24 bits. 2. SFR is loaded from the reset vector. 3. All bits except F1, F0, and P are loaded from the reset vector. Those bits are all 0. 4. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other purposes in future XA derivatives. The reset value shown for these bits is 0. 5. Port configurations default to quasi-bidirectional when the XA begins execution from internal code memory after reset, based on the condition found on the EA pin. Thus, all PnCFGA registers will contain FF, and PnCFGB register will contain 00 when the XA begins execution using internal code memory. When the XA begins execution using external code memory, the default configuration for pins that are associated with the external bus will be push-pull. The PnCFGA and PnCFGB register contents will reflect this difference. 6. The WDCON reset value is E6 for a Watchdog reset, E4 for all other reset causes. 7. The RSTSRC register reflects the cause of the last XA-S3 reset. One bit will be set to 1, the others will be cleared to 0. 8. The XA guards writes to certain bits (typically interrupt flags) that may be altered directly by a peripheral function. This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action during the time between the read and write portions of an instruction that performs a read-modify-write operation. Examples of such instructions are: and s0con,#$fb clr tr0 setb ti_0 XA-S3 SFR bits that are guarded in this manner are: ADINT (in ADCON); CF, CCF4, CCF3, CCF2, CCF1, and CCF0 (in CCON); SI (in I2CON); TI_0 and RI_0 (in S0CON); TI_1 and RI_1 (in S1CON); FE0, BR0, and OE0 (in S0STAT); FE1, BR1, and OE1 (in S1STAT); TF2 (in T2CON); TF1, TF0, IE1, and IE0 (in TCON); and WDTOF (in WDCON). 9. The XA-S3 implements an 8-bit SFR bus, as stated in Chapter 8 of the XA User Guide. All SFR accesses must be 8-bit operations. Attempts to write 16 bits to an SFR will actually write only the lower 8 bits. Sixteen bit SFR reads will return undefined data in the upper byte.
2000 Dec 01
12
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
FFFFFh
Up to 16 MB Total Code Memory
8000h 7FFFh 32 kB On-chip Code Memory 0000h
SU01219
Figure 1. XA-S3 program memory map
Data Segment 0 FFFFh FFFFh
Other Data Segments
Data Memory (Indirectly Addressed, Off-Chip)
Data Memory (Indirectly Addressed, Off-Chip)
0400h 03FFh Data Memory (Directly or Indirectly Addressable, On-Chip 1 kB On-Chip Data Memory (RAM) (Bit-Addressable Data Area) Data Memory (Directly or Indirectly Addressable, On-Chip 0000h 0040h 003Fh 0020h 001Fh Directly Addressed Data (1 k per Segment)
0400h 03FFh Data Memory (Directly or Indirectly Addressable, On-Chip 0040h 003Fh 0020h 001Fh (Bit-Addressable Data Area) Data Memory (Directly or Indirectly Addressable, Off-Chip 0000h
SU01220
Figure 2. XA-S3 data memory map
2000 Dec 01
13
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
FUNCTIONAL DESCRIPTION
Details of XA-S3 functions will be described in the following sections.
of register ADRSL. These bits must be read before another conversion is begun. A/D conversions are begun by setting the A/D Start and STatus bit in ADCON. In the single scan mode, all of the channels selected by bits in the ADCS register will be converted once. The ADINT flag is set when the last channel is converted. In the continuous scan mode, the A/D converter continuously converts all A/D channels selected by bits in the ADCS register. The ADINT flag is set when all channels have been converted once. The A/D converter can generate an interrupt when the ADINT flag is set. This will occur if the A/D interrupt is enabled (via the EAD bit in IEL), the interrupt system is enabled (via the EA bit in IEL), and the A/D interrupt priority (specified in IPA3 bits 3 to 0) is higher than the currently running code (PSW bits IM3 through IM0) and any other pending interrupt. ADINT must be cleared by software. A/D Timing Configuration The A/D sampling and conversion timing may be optimized for the particular oscillator frequency and input drive characteristics of the application. Because A/D operation is mostly dependent on real-time effects (charging time of sampling capacitors, settling time of the comparator, etc.), A/D conversion times are not necessarily much longer at slower clock frequencies. The A/D timing is controlled by the ADCFG register, as shown in Figure 3, Table 2 and Table 3. The primary effect of ADCFG settings is to adjust the A/D sample and hold time to be relatively constant over various clock frequencies. Two settings (value 6 and B) are provided to allow fast conversions with a lower external source driving the A/D inputs. These settings provide double the sample time at the same frequency. Of course, settings intended for lower frequencies may also be used at higher frequencies in order to increase the A/D sampling time, but this method has the side effect of significantly increasing A/D conversion times.
Analog to Digital converter
The XA-S3 has an 8-channel, 8-bit A/D converter with 8 sets of result registers, single scan and multiple scan operating modes. The A/D also has a 10-bit conversion mode that provides greater result resolution. The A/D input range is limited to 0 to AVDD (3.3 V max.). The A/D inputs are on Port 5. Analog Power and Ground as well as AVREF+ and AVREF- must be supplied in order for the A/D converter to be used. Prior to enabling the A/D converter or driving analog signals into the A/D inputs, the port configurations for the pins being used as A/D inputs must be set to the "off" (high impedance, input only) mode. A/D timing can be adapted to the application clock frequency in order to provide the fastest possible conversion. A/D converter operation is controlled through the ADCON (A/D Control) register, see Figure 1. Bits in ADCON start and stop the A/D, flag conversion completion, and select the converter operating modes. When 10-bit resolution is needed, the A/D mode may be set to give 10 result bits by setting the ADRES bit to 1. In this mode, the A/D takes longer to complete a conversion, and the timing must be set differently in ADCFG. A/D Conversion Modes The A/D converter supports a single scan mode and a continuous scan mode. In either mode, one or more A/D channels may be converted. The ADCS register determines which channels are converted. If the corresponding bit in the ADCS register is set, that channel is selected for conversions, otherwise that channel is skipped. The ADCS register is detailed in Figure 2. For any A/D conversion, the results are stored in ADRSHn, corresponding to the A/D channel just converted. For a 10-bit conversion, the two least significant bits are read from the upper end
ADCON Address:43Eh Bit Addressable Reset Value: 00h BIT ADCON.7 ADCON.6 ADCON.5 ADCON.4 ADCON.3 ADCON.2 SYMBOL -- -- -- -- ADRES ADMOD
MSB -- -- -- -- ADRES ADMOD ADSST
LSB ADINT
ADCON.1
ADSST
ADCON.0
ADINT
FUNCTION Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Selects 8-bit (0) or 10-bit (1) conversion mode. A/D mode select. 1 = continuous scan of selected inputs after a start of the A/D. 0 = single scan of selected inputs after a start of the A/D. A/D start and status. Setting this bit by software starts the A/D conversion of the selected A/D inputs. ADSST remains set as long as the A/D is in operation. In continuous conversion mode, ADSST will remain set unless the A/D is stopped by software. While ADSST is set, new start commands are ignored. An A/D conversion is progress may be aborted by software clearing ADSST. A/D conversion complete/interrupt flag. This flag is set when all selected A/D channels are converted in either the single scan or continuous scan modes. Must be cleared by software.
SU01229
Figure 1. A/D Control Register (ADCON)
2000 Dec 01
14
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
ADCS Address:43Fh Bit Addressable Reset Value: 00h BIT ADCS.7 ADCS.6 ADCS.5 ADCS.4 ADCS.3 ADCS.2 ADCS.1 ADCS.0 SYMBOL ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
MSB
LSB
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 FUNCTION A/D channel 7 select bit. A/D channel 6 select bit. A/D channel 5 select bit. A/D channel 4 select bit. A/D channel 3 select bit. A/D channel 2 select bit. A/D channel 1 select bit. A/D channel 0 select bit. Figure 2. A/D Channel Select Register (ADCS)
SU00939
ADCFG Address:4B9h Not bit Addressable Reset Value: 00h BIT ADCFG.7 ADCFG.6 ADCFG.5 ADCFG.4 ADCFG.3-0 SYMBOL -- -- -- -- ADCFG
MSB -- -- -- -- A/D Timing Configuration
LSB
FUNCTION Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. A/D timing configuration (see text and table).
SU00940
Figure 3. A/D Timing Configuration Register (ADCFG)
Table 2. A/D Timing Configuration
ADCFG.3-0 ADCFG 3 0 0h (0000) 1h (0001) 2h (0010) 3h (0011) 4h (0100) 5h (0101) 6h (0110)1 7h (0111) 8h (1000) 9h (1001) Ah (1010) Bh (1011)1 Max. Oscillator Frequency (MHz) 6.66 10 11.11 13.33 16.66 20 20 22.2 23.3 26.6 30 30 - - - - Conversion Time Osc. Clocks 72 76 80 96 100 104 116 108 124 128 132 146 136 152 172 176 sec at max. Osc. 10.81 7.6 7.2 7.2 6.0 5.2 5.8 4.86 5.32 4.81 4.4 4.87 4.25 4.56 4.7 4.4 Sampling Time pg (Osc. Clocks) 4 6 8 8 10 12 24 14 14 16 18 32 20 20 22 24
Ch (1100) Dh (1101) Eh (1110) Fh (1111)
NOTE: 1. These settings provide additional A/D input sampling time, in order to allow accurate readings with a higher external source impedance.
2000 Dec 01
15
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
Table 3. A/D Timing Configuration for 10-bit Mode
ADCFG.3-0 ADCFG 3 0 0h (0000) 1h (0001) 2h (0010) 3h (0011) 4h (0100) 5h (0101) 6h (0110) 7h (0111) 8h (1000) 9h (1001) Ah (1010) Bh (1011) Ch (1100) Dh (1101) Eh (1110) Fh (1111) Max. Oscillator Frequency (MHz) 6.66 8 8 12 12 12 12 12 13 13 13 13 13 16 20 20 Conversion Time Osc. Clocks 88 92 96 116 120 124 136 128 148 152 156 170 160 180 204 208 sec at max. Osc. 13.21 9.2 8.64 8.7 7.2 6.2 6.8 5.77 6.35 5.71 5.2 5.67 5.0 5.41 5.57 5.2 Sampling Time pg (Osc. Clocks) 4 6 8 8 10 12 24 14 14 16 18 32 20 20 22 24
A/D Inputs In order to obtain accurate measurements with the A/D Converter, the source drive must be sufficient to adequately charge the sampling capacitor during the sampling time. Figure 4 shows the equivalent resistance and capacitance related to the A/D inputs. A/D timing configurations indicated in Table 1 allow for full A/D
accuracy (according to the A/D specifications) assuming a source resistance of less than or equal to 20k. Larger source resistances may be accommodated by increasing the sampling time with a different A/D timing configuration.
SmN+1 ADN+1 SmN
RmN+1
ADN
+
RmN
TO COMPARATOR
Multiplexer
RS VANALOG
INPUT
CS
CC
Rm (multiplexer resistance) CS (pin capacitance) CC (sampling capacitor) RS (source resistance)
= = = =
3 k maximum 10 pF maximum 2 pF maximum Recommended less than 20k for full specified accuracy. This allows time for the sampling capacitor (CC) to fully charge while the multiplexer switch is closed. Please note that sampling causes the analog input to present a varying load to the pin.
SU00948
Figure 4. A/D Input: Equivalent Circuit
2000 Dec 01
16
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
A/D Accuracy The XA-S3 A/D in 10 -bit mode is specified with 16 samples averaged in order to factor out on-chip noise. In an application where averaging 16 samples is not practical, the accuracy specifications may be de-rated according to the number of samples 1.50 1.25 Additional Error (LSB) 1.00 0.75 0.50 0.25 0.00 1 2 3 4 5 6 7 8
that are actually taken. The graph in Figure 5 shows the relationship of additional A/D error to the number of samples that are averaged. For example, if a single A/D reading is used with no averaging, the A/D accuracy should be de-rated by 1.25 LSB.
9
10
11
12
13
14
15
16
Number of Samples Figure 5. A/D accuracy by number of averaging samples (Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to fC = 20 MHz.)
SU01227
I2CON Address:42Ch Bit Addressable Reset Value: 00h BIT I2CON.7 I2CON.6 I2CON.5 I2CON.4 I2CON.3 I2CON.2 I2CON.1 I2CON.0 SYMBOL CR2 ENA STA STO SI AA CR1 CR0
MSB CR2 ENA STA STO SI AA CR1
LSB CR0
FUNCTION I2C Rate Control, with CR1 and CR0. See text and table. Enable I2C port. When ENA = 1, the I2C port is enabled. Start flag. Setting STA to 1 causes the I2C interface to attempt to gain mastership of the bus by generating a Start condition. Stop flag. Setting STO to 1 causes the I2C interface to attempt to generate a Stop condition. Serial Interrupt. SI is set by the I2C hardware when a new I2C state is entered, indicating that software needs to respond. SI causes an I2C interrupt if enabled and of sufficient priority. Assert Acknowledge. Setting AA to 1 causes the I2C hardware to automatically generate acknowledge pulses for various conditions (see text). I2C Rate Control, with CR2 and CR0. See text and table. I2C Rate Control, with CR2 and CR1. See text and table.
SU00941
Figure 6.
I2 C
Control Register (I2CON)
2000 Dec 01
17
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
I2C Interface
The I2C interface on the XA-S3 is identical to the standard byte-style I2C interface found on devices such as the 8xC552 except for the rate selection. The I 2C interface conforms to the 100 kHz I 2C specification, but may be used at rates up to 400 kHz (non-conforming). Important: Before the I2C interface may be used, the port pins P5.6 and 5.7, which correspond to the I2C functions SCL and SDA respectively, must be set to the open drain mode. The processor interfaces to the I2C logic via the following four special function registers: I2CON (I2C control register), I2STA (I2C status register), I2DAT (I2C data register), and I2ADR (I2C slave address register). The I2C control logic interfaces to the external I2C bus via two port 5 pins: P5.6/SCL (serial clock line) and P5.7/SDA (serial data line). The Control Register, I2CON This register is shown in Figure 6. Two bits are affected by the I2C hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when a STOP condition is present on the I2C bus. The STO bit is also cleared when ENA = "0". ENA, the I2C Enable Bit ENA = 0: When ENA is "0", the SDA and SCL outputs are not driven. SDA and SCL input signals are ignored, SIO1 is in the "not addressed" slave state, and the STO bit in I2CON is forced to "0". No other bits are affected. P5.6 and P5.7 may be used as open drain I/O ports. ENA = 1: When ENA is "1", SIO1 is enabled. The P5.6 and P5.7 port latches must be set to logic 1. ENA should not be used to temporarily release the I2C-bus since, when ENA is reset, the I2C-bus status is lost. The AA flag should be used instead (see description of the AA flag in the following text). In the following text, it is assumed the ENA = "1". STA, the START flag STA = 1: When the STA bit is set to enter a master mode, the I2C hardware checks the status of the I2C bus and generates a START condition if the bus is free. If the bus is not free, the I2C interface waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal serial clock generator. If STA is set while the I2C interface is already in a master mode and one or more bytes are transmitted or received, the hardware transmits a repeated START condition. STA may be set at any time. STA may also be set when the I2C interface is an addressed slave. STA = 0: When the STA bit is reset, no START condition or repeated START condition will be generated. STO, the STOP flag STO = 1: When the STO bit is set while the I2C interface is in a master mode, a STOP condition is transmitted to the I2C bus. When the STOP condition is detected on the bus, the hardware clears the STO flag. In a slave mode, the STO flag may be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C bus. However, the hardware behaves as if a STOP condition has been received and switches to the defined "not addressed" slave receiver mode. The STO flag is automatically cleared by hardware.
If the STA and STO bits are both set, then a STOP condition is transmitted to the I2C bus if the interface is in a master mode (in a slave mode, the hardware generates an internal STOP condition which is not transmitted). The I2C interface then transmits a START condition. STO = 0: When the STO bit is reset, no STOP condition will be generated. SI, the Serial Interrupt flag SI = 1: When the SI flag is set, and the EA (interrupt system enable) and EI2 (I2C interrupt enable) bits are also set, an I2C interrupt is requested. SI is set by hardware when one of 25 of the 26 possible I2C interface states is entered. The only state that does not cause SI to be set is state F8H, which indicates that no relevant state information is available. While SI is set, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must be reset by software. SI = 0: When the SI flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the SCL line. AA, the Assert Acknowledge flag AA = 1: If the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when:
* The "own slave address" has been received. * The general call address has been received while the general call
bit (GC) in I2ADR is set.
* A data byte has been received while the I2C interface is in the
master receiver mode.
* A data byte has been received while the I2C interface is in the
addressed slave receiver mode. AA = 0: If the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: master receiver mode.
* A data byte has been received while the I2C interface is in the * A data byte has been received while the I2C interface is in the
addressed slave receiver mode.
When the I2C interface is in the addressed slave transmitter mode, state C8H will be entered after the last serial data byte is transmitted. When SI is cleared, the I2C interface leaves state C8H, enters the not addressed slave receiver mode, and the SDA line remains at a high level. In state C8H, the AA flag can be set again for future address recognition. When the I2C interface is in the not addressed slave mode, its own slave address and the general call address are ignored. Consequently, no acknowledge is returned, and a serial interrupt is not requested. Thus, the hardware can be temporarily released from the I2C bus while the bus status is monitored. While the hardware is released from the bus, START and STOP conditions are detected, and serial data is shifted in. Address recognition can be resumed at any time by setting the AA flag. If the AA flag is set when the part's own slave address or the general call address has been partly received, the address will be recognized at the end of the byte transmission.
2000 Dec 01
18
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CR0, CR1, and CR2, the Clock Rate Bits These three bits determine the serial clock frequency when the I2C interface is in a master mode. An I2C rate of 100kHz or lower is typical and can be derived from many oscillator frequencies. The various serial rates are shown in Table 4. A variable bit rate may also be used if Timer 1 is not required for any other purpose while the I2C hardware is in a master mode. The frequencies shown in Table 4 are unimportant when the I2C hardware is in a slave mode. In the slave modes, the hardware will automatically synchronize with the incoming clock frequency.
The I2C Status Register, I2STA
I2STA is an 8-bit read-only special function register. The three least significant bits are always zero. The five most significant bits contain the status code. There are 26 possible status codes. When I2STA contains F8H, no relevant state information is available and no serial interrupt is requested. All other I2STA values correspond to defined hardware interface states. When each of these states is entered, a serial interrupt is requested (SI = "1"). NOTE: A detailed I2C interface description and usage information, including example driver code, will be provided in a separate document.
Table 4. I2C Rate Control
Frequency Select q y (CR2, CR1, CR0) 0h (0000) 1h (0001) 2h (0010) 3h (0011) 4h (0100) 5h (0101) 6h (0110) 7h (0111) Example I2C Rates at Specific Oscillator Frequencies Clock Divisor 20 40 68 88 160 272 352 (Timer 1)2 8 MHz (400)1 (200)1 (116.65)1 90.91 50 29.41 22.73 (Timer 1)2 12 MHz - (300)1 (176.46)1 (136.36)1 75 44.12 34.09 (Timer 1)2 16 MHz - (400)1 (235.29)1 (181.82)1 100 58.82 45.45 (Timer 1)2 20 MHz - - (294.12)1 (227.27)1 (125)1 73.53 56.82 (Timer 1)2 24 MHz - - (352.94)1 (272.73)1 (150)1 88.24 68.18 (Timer 1)2 30 MHz - - - (340.91)1 (187.5)1 (110.29)1 85.23 (Timer 1)2
NOTES: 1. The XA-S3 I2C interface does not conform to the 400kHz I2C specification (which applies to rates greater than 100kHz) in all details, but may be used with care where higher rates are required by the application. 2. The timer 1 overflow is used to clock the I2C interface. The resulting bit rate is 1/2 of the timer overflow rate.
2000 Dec 01
19
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
XA-S3 Timer/Counters
The XA-S3 has three general purpose counter/timers, two of which may also be used as baud rate generators for either or both of the UARTs. Timer 0 and 1 These are identical to the standard XA-G3 timer 0 and 1. Timer 2 This is identical to the standard XA-G3 timer 2.
Programmable Counter Array (PCA)
The Programmable Counter Array available on the XA-S3 is a special 16-bit Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P4.1(CEX0), module 1 to P4.2(CEX1), etc. The basic PCA configuration is shown in Figure 7. The PCA timer is a common time base for all five modules and can be programmed to run at: the TCLK rate (Osc/4, Osc/16, or Osc/64), the Timer 0 overflow, or the input on the ECI pin (P4.0). When the ECI input is used, the falling edge clocks the PCA counter. The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 10): CPS1 CPS0 PCA Timer Count Source 0 X TCLK (Osc/4, Osc/16, or Osc/64) 1 0 Timer 0 overflow 1 1 ECI (PCA External Clock Input (max rate = Osc/4) In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 8. In addition, each PCA module may generate a separate interrupt. The watchdog timer function is implemented in module 4 (see Figure 17).
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 11). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 9. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 12). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 13 shows the CCAPMn settings for the various PCA functions. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output.
16 BITS MODULE 0 P4.1/CEX0
MODULE 1 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) MODULE 2
P4.2/CEX1
P4.3/CEX2
P4.4/CEX3
MODULE 4
P4.5/CEX4
SU01303
Figure 7. Programmable Counter Array (PCA)
2000 Dec 01
20
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
TO PCA MODULES
TCLK (OSC/4, OSC/16, OR OSC/64) TIMER 0 OVERFLOW EXTERNAL INPUT (P4.0/ECI) 01 10 11
OVERFLOW CH CL INTERRUPT
16-BIT UP COUNTER
DECODE
IDLE CIDL WDTE -- -- -- CPS1 CPS0 ECF CMOD (490H)
CF
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (41AH)
SU01304
Figure 8. PCA Timer/Counter
CF PCA TIMER/COUNTER
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (41AH)
MODULE 0 IEL.5 EPC MODULE 1 IEL.7 EA TO INTERRUPT PRIORITY DECODER
MODULE 2
MODULE 3
MODULE 4
CMOD.0
ECF
CCAPMn.0
ECCFn
SU01305
Figure 9. PCA Interrupt System
2000 Dec 01
21
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CMOD Address = 490H
Reset Value = 00H
CIDL Bit: Symbol CIDL WDTE - CPS1 CPS0 Function 7
WDTE 6
- 5
- 4
- 3
CPS1 2
CPS0 1
ECF 0
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. Not implemented, reserved for future use.* PCA Count Pulse Select bit 1. PCA Count Pulse Select bit 0. CPS1 0 1 1 CPS0 X 0 1 PCA Timer Count Source TClk (Osc/4, Osc/16, or Osc/64) Timer 0 overflow ECI (PCA External Clock Input (max rate = Osc/4)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.
NOTE: * User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** fOSC = oscillator frequency
SU01306
Figure 10. CMOD: PCA Counter Mode Register
CCON Address = 41AH Bit Addressable CF Bit: Symbol CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Function 7 CR 6 - 5 CCF4 4 CCF3 3 CCF2 2 CCF1 1 CCF0 0
Reset Value = 00H
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use*. PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector.
NOTE: * User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01307
Figure 11. CCON: PCA Counter Control Register
2000 Dec 01
22
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CCAPMn Address
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
491H 492H 493H 494H 495H
Reset Value = 00H
Not Bit Addressable - Bit: Symbol - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 7 ECOMn 6 CAPPn 5 CAPNn 4 MATn 3 TOGn 2 PWMn 1 ECCFn 0
NOTE: *User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU01308
Figure 12. CCAPMn: PCA Modules Compare/Capture Registers - X X X X X X X X ECOMn 0 X X X 1 1 1 1 CAPPn 0 1 0 1 0 0 0 0 CAPNn 0 0 1 1 0 0 0 0 MATn 0 0 0 0 1 1 0 1 TOGn 0 0 0 0 0 1 0 X PWMn 0 0 0 0 0 0 1 0 ECCFn 0 X X X X X 0 X No operation 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit PWM Watchdog Timer MODULE FUNCTION
Figure 13. PCA Module Modes (CCAPMn Register) PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 14. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 15). High Speed Output Mode In this mode the CEX output (on port 4) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (see Figure 16). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 17 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
2000 Dec 01
23
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CF
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (41AH)
PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL
CEXn
CAPTURE
CCAPnH
CCAPnL
--
ECOMn 0
CAPPn
CAPNn
MATn 0
TOGn 0
PWMn 0
ECCFn
CCAPMn, n= 0 to 4 (491H-495H)
SU01309
Figure 14. PCA Capture Mode
CF WRITE TO CCAPnH RESET
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (41AH)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnH
CCAPnL
PCA INTERRUPT (TO CCFn)
16-BIT COMPARATOR
MATCH
CH
CL
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn
TOGn 0
PWMn 0
ECCFn
CCAPMn, n= 0 to 4 (491H-495H)
SU01310
Figure 15. PCA Compare Mode
2000 Dec 01
24
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CF WRITE TO CCAPnH RESET CCAPnH
CR
--
CCF4
CCF3
CCF2
CCF1
CCF0
CCON (41AH)
WRITE TO CCAPnL 0 1 ENABLE
CCAPnL
PCA INTERRUPT (TO CCFn)
MATCH 16-BIT COMPARATOR
TOGGLE CH CL CEXn
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn
TOGn 1
PWMn 0
ECCFn
CCAPMn, n: 0..4 (491H-495H)
SU01311
Figure 16. PCA High Speed Output Mode
CCAPnH
CCAPnL 0 CL < CCAPnL ENABLE 8-BIT COMPARATOR CL >= CCAPnL 1 OVERFLOW CL PCA TIMER/COUNTER CEXn
--
ECOMn
CAPPn 0
CAPNn 0
MATn 0
TOGn 0
PWMn
ECCFn 0
CCAPMn, n: 0..4 (491H-495H)
SU01312
Figure 17. PCA PWM Mode
2000 Dec 01
25
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CIDL WRITE TO CCAP4H RESET
WDTE
--
--
--
CPS1
CPS0
ECF
CMOD (490H)
WRITE TO CCAP4L 0 1 ENABLE
CCAP4H
CCAP4L
MODULE 4
MATCH 16-BIT COMPARATOR RESET
CH
CL
PCA TIMER/COUNTER
--
ECOMn
CAPPn 0
CAPNn 0
MATn 1
TOGn X
PWMn 0
ECCFn X
CCAPM4 (495H)
SU01313
Figure 18. PCA Watchdog Timer m(Module 4 only) PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 18 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven low. In order to hold off the reset, the user has three options: 1. periodically change the compare value so it will never match the PCA timer, 2. periodically change the PCA timer value so it will never match the compare values, or 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. Figure 19 shows the code for initializing the watchdog timer. Module 4 can be configured in either compare mode, and the WDTE bit in CMOD must also be set. The user's software then must periodically change (CCAP4H,CCAP4L) to keep a match from occurring with the PCA timer (CH,CL). This code is given in the WATCHDOG routine in Figure 19. This routine should not be part of an interrupt service routine, because if the program counter goes astray and gets stuck in an infinite loop, interrupts will still be serviced and the watchdog will keep getting reset. Thus, the purpose of the watchdog would be defeated. Instead, call this subroutine from the main program within 216 count of the PCA timer.
2000 Dec 01
26
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
INIT_WATCHDOG: MOV CCAPM4, #4CH MOV CCAP4L, #0FFH MOV CCAP4H, #0FFH
OR CMOD, #40H
; ; ; ; ; ; ; ;
Module 4 in compare mode Write to low byte first Before PCA timer counts up to FFFF Hex, these compare values must be changed Set the WDTE bit to enable the watchdog timer without changing the other bits in CMOD
; ;******************************************************************** ; ; Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H, CH ; 255 counts of the current PCA SETB EA ; timer value RET Figure 19. PCA Watchdog Timer Initialization Code
Watchdog Timer
This is a standard XA-G3 watchdog timer. This watchdog timer always comes up running at reset. The watchdog acts the same on EPROM, ROM, and ROMless parts, as in the XA-G3.
transmit register, and reading SnBUF accesses a physically separate receive register. The serial port can operate in 4 modes: Mode 0: Serial I/O expansion mode. Serial data enters and exits through RxDn. TxDn outputs the shift clock. 8 bits are transmitted/received (LSB first). (The baud rate is fixed at 1/16 the oscillator frequency.) Mode 1: Standard 8-bit UART mode. 10 bits are transmitted (through TxDn) or received (through RxDn): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SnCON. The baud rate is variable. Mode 2: Fixed rate 9-bit UART mode. 11 bits are transmitted (through TxD) or received (through RxD): start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On Transmit, the 9th data bit (TB8_n in SnCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8_n. On receive, the 9th data bit goes into RB8_n in Special Function Register SnCON, while the stop bit is ignored. The baud rate is programmable to 1/32 of the oscillator frequency. Mode 3: Standard 9-bit UART mode. 11 bits are transmitted (through TxDn) or received (through RxDn): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SnBUF as a destination register. Reception is initiated in Mode 0 by the condition RI_n = 0 and REN_n = 1. Reception is initiated in the other modes by the incoming start bit if REN_n = 1.
UARTs
Standard XA-S3 UART0 and UART1 with double buffered transmit register. A flag has been added to SnSTAT that is set if any of the status flags (BRn, FEn, or OEn) is set for the corresponding UART channel. This allows polling for UART errors quickly at the interrupt service routine. Baud rate sources may be timer 1 or timer 2. The XA-S3 includes 2 UART ports that are compatible with the enhanced UART used on the XA-G3. The UART has separate interrupt vectors for each UART's transmit and receive functions. The UART transmitter has been double buffered, allowing packed transmission of data with no gaps between bytes and less critical interrupt service routine timing. A break detect function has been added to the UART. This operates independently of the UART itself and provides a start-of-break status bit that the program may test. An Overrun Error flag allows detection of missed characters in the received data stream. The double buffered UART transmitter may require some software changes if code is used that was written for the original XA-G3 single buffered UART. Each UART baud rate is determined by either a fixed division of the oscillator (in UART modes 0 and 2) or by the timer 1 or timer 2 overflow rate (in UART modes 1 and 3). Timer 1 defaults to clock both UART0 and UART1. Timer 2 can be programmed to clock either UART0 through T2CON (via bits R0CLK and T0CLK) or UART1 through T2MOD (via bits R1CLK and T1CLK). In this case, the UART not clocked by T2 could use T1 as the clock source. The serial port receive and transmit registers are both accessed at Special Function Register SnBUF. Writing to SnBUF loads the
2000 Dec 01
27
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
Serial Port Control Register The serial port control and status register is the Special Function Register SnCON, shown in Figure 21. This register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n and RI_n). TI Flag In order to allow easy use of the double buffered UART transmitter feature, the TI_n flag is set by the UART hardware under two conditions. The first condition is the completion of any byte transmission. This occurs at the end of the stop bit in modes 1, 2, or 3, or at the end of the eighth data bit in mode 0. The second condition is when SnBUF is written while the UART transmitter is idle. In this case, the TI_n flag is set in order to indicate that the second UART transmitter buffer is still available. Typically, UART transmitters generate one interrupt per byte transmitted. In the case of the XA UART, one additional interrupt is generated as defined by the stated conditions for setting the TI_n flag. This additional interrupt does not occur if double buffering is bypassed as explained below. Note that if a character oriented approach is used to transmit data through the UART, there could be a second interrupt for each character transmitted, depending on the timing of the writes to SBUF. For this reason, it is generally better to bypass double buffering when the UART transmitter is used in character oriented mode. This is also true if the UART is polled rather than interrupt driven, and when transmission is character oriented rather than message or string oriented. The interrupt occurs at the end of the last byte transmitted when the UART becomes idle. Among other things, this allows a program to determine when a message has been transmitted completely. The interrupt service routine should handle this additional interrupt. The recommended method of using the double buffering in the application program is to have the interrupt service routine handle a single byte for each interrupt occurrence. In this manner the program essentially does not require any special considerations for double buffering. Unless higher priority interrupts cause delays in the servicing of the UART transmitter interrupt, the double buffering will result in transmitted bytes being tightly packed with no intervening gaps. 9-bit Mode Please note that the ninth data bit (TB8) is not double buffered. Care must be taken to insure that the TB8 bit contains the intended data at the point where it is transmitted. Double buffering of the UART transmitter may be bypassed as a simple means of synchronizing TB8 to the rest of the data stream. Bypassing Double Buffering The UART transmitter may be used as if it is single buffered. The recommended UART transmitter interrupt service routine (ISR) technique to bypass double buffering first clears the TI_n flag upon entry into the ISR, as in standard practice. This clears the interrupt that activated the ISR. Secondly, the TI_n flag is cleared immediately following each write to SnBUF. This clears the interrupt flag that would otherwise direct the program to write to the second transmitter buffer. If there is any possibility that a higher priority interrupt might become active between the write to SnBUF and the clearing of the TI_n flag, the interrupt system may have to be temporarily disabled during that sequence by clearing, then setting the EA bit in the IEL register.
CLOCKING SCHEME/BAUD RATE GENERATION
The XA UARTS clock rates are determined by either a fixed division (modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2 overflow rate (modes 1 and 3). The clock for the UARTs in XA runs at 16x the Baud rate. If the timers are used as the source for Baud Clock, since maximum speed of timers/Baud Clock is Osc/4, the maximum baud rate is timer overflow divided by 16 i.e. Osc/64. In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate is Osc/32. 00 Pre-scaler for all Timers T0,1,2 T0 1 2 controlled by PT1, PT0 bits in SCR 01 10 11 Osc/4 Osc/16 Osc/64 reserved
Baud Rate for UART Mode 0: Baud_Rate = Osc/16 Baud Rate calculation for UART Mode 1 and 3: Baud_Rate = Timer_Rate/16 Timer_Rate = Osc/(N*(Timer_Range- Timer_Reload_Value)) where N = the TCLK prescaler value: 4, 16, or 64. and Timer_Range = 256 for timer 1 in mode 2. 65536 for timer 1 in mode 0 and timer 2 in count up mode. The timer reload value may be calculated as follows: Timer_Reload_Value = Timer_Range-(Osc/(Baud_Rate*N*16)) NOTES: 1.. The maximum baud rate for a UART in mode 1 or 3 is Osc/64. 2.. The lowest possible baud rate (for a given oscillator frequency and N value) may be found by using a timer reload value of 0. 3.. The timer reload value may never be larger than the timer range. 4.. If a timer reload value calculation gives a negative or fractional result, the baud rate requested is not possible at the given oscillator frequency and N value. Baud Rate for UART Mode 2: Baud_Rate = Osc/32
Using Timer 2 to Generate Baud Rates
Timer T2 is a 16-bit up/down counter in XA. As a baud rate generator, timer 2 is selected as a clock source for either/both UART0 and UART1 transmitters and/or receivers by setting TCLKn and/or RCLKn in T2CON and T2MOD. As the baud rate generator, T2 is incremented as Osc/N where N = 4, 16 or 64 depending on TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is the source of one UART, the other UART could be clocked by either T1 overflow or fixed clock, and the UARTs could run independently with different baud rates. T2CON 0x418 bit5 RCLK0 bit5 RCLK1 bit4 TCLK0 bit4 TCLK1
T2MOD 0x419
Prescaler Select for Timer Clock (TCLK) SCR 0x440 bit3 PT1 bit2 PT0
2000 Dec 01
28
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
SnSTAT Address: S0STAT 421 S1STAT 425 Bit Addressable Reset Value: 00H
MSB -- -- -- -- FEn BRn OEn
LSB STINTn
BIT SYMBOL FUNCTION SnSTAT.3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. Cleared by software. SnSTAT.2 BRn Break Detect flag is set if a character is received with all bits (including STOP bit) being logic `0'. Thus it gives a "Start of Break Detect" on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect feature operates independently of the UARTs and provides the START of Break Detect status bit that a user program may poll. Cleared by software. SnSTAT.1 OEn Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while RI in SnCON is still set. Cleared by software. SnSTAT.0 STINTn This flag must be set to enable any of the above status flags to generate a receive interrupt (RIn). The only way it can be cleared is by a software write to this register. Figure 20. Serial Port Extended Status (SnSTAT) Register (See also Figure 22 regarding Framing Error flag)
SU00607B
UART INTERRUPT SCHEME
There are separate interrupt vectors for each UART's transmit and receive functions.
Error (FE) flag. In a Mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 23. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X
Table 5. Interrupt Vector Locations for UARTs
Vector Address A0H - A3H A4H - A7H A8H - ABH ACH - AFH Interrupt Source UART 0 Receiver UART 0 Transmitter UART 1 Receiver UART 1 Transmitter Arbitration 9 10 11 12
NOTE: The transmit and receive vectors could contain the same ISR address to work like a 8051 interrupt scheme Error Handling, Status Flags and Break Detect XA UARTs have several error flags as described in Figures 20 and 22.
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit although this is better done with the Framing
Slave 1
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
2000 Dec 01
29
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.
Slave 1
Slave 2
SnCON
Address:
S0CON 420 S1CON 424
MSB SM0 SM1 SM2 REN TB8 RB8 TI
LSB RI
Bit Addressable Reset Value: 00H SM0 0 0 1 1
Where SM0, SM1 specify the serial port mode, as follows: SM1 0 1 0 1 Mode 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate fOSC/16 variable fOSC/32 variable
BIT SYMBOL FUNCTION SnCON.5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not received. In Mode 0, SM2 should be 0. SnCON.4 REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. SnCON.3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. The TB8 bit is not double buffered. See text for details. SnCON.2 RB8 In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, if SM2=0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. SnCON.1 TI Transmit interrupt flag. Set when another byte may be written to the UART transmitter. See text for details. Must be cleared by software. SnCON.0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the end of the stop bit time in the other modes (except see SM2). Must be cleared by software.
SU00597C
Figure 21. Serial Port Control (SnCON) Register
2000 Dec 01
30
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
if 0, sets FE
--
--
--
--
FEn
BRn
OEn
STINTn
SnSTAT
SU00598
Figure 22. UART Framing Error Detection
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0_n 1 1
SM1_n 1 0
SM2_n 1
REN_n 1
TB8_n X
RB8_n
TI_n
RI_n
SnCON
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00613
Figure 23. UART Multiprocessor Communication, Automatic Address Recognition
Clocking / Baud Rate Generation
Same as for the XA-G3.
I/O Port Output Configuration
Port output configurations are the same as for the XA-G3: open drain, quasi-bidirectional, push-pull, and off.
The latched values of EA and BUSW are NOT automatically updated when an internal reset occurs. RSTOUT may be used to apply an external reset to the XA-S3 in order to update the previously latched EA and BUSW values. However, since RSTOUT reflects ALL reset sources, it cannot simply be fed back into the RST pin without other logic. The reset source identification register (RSTSRC) indicates the cause of the most recent XA reset. The cause may have been an externally applied reset signal, execution of the RESET instruction, or a Watchdog reset. Figure 24 shows the fields in the RSTSRC register.
External Bus
The external bus operates in the same manner as the XA-G3, but all 24 address lines are brought out to the outside world. This allows for a maximum of 16 Mbytes of code memory and 16 Mbytes of data memory.
Power Reduction Modes
The XA-S3 supports Idle and Power Down modes of power reduction. The idle mode leaves some peripherals running in order to allow them to activate the processor when an interrupt is generated. The power down mode stops the oscillator in order to absolutely minimize power. The processor can be made to exit power down mode via a reset or one of the external interrupt inputs (INT0 or INT1). This will occur if the interrupt is enabled and its priority is higher than that defined by IM3 through IM0. In power down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM, register, and SFR contents at the point where power down mode was entered. VDD must be raised to within the operating range before power down mode is exited.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some situations. This output reflects the X1 clock input to the XA, but is delayed to match the external bus outputs and strobes. The default is for CLKOUT to be on at reset, but it may be turned off via the CLKD bit that has been added to the BCR register.
Reset
Active low reset input, the same as the XA-G3. The associated RSTOUT pin provides an external indication via an active low open drain output when an internal reset occurs. The RSTOUT pin will be driven low when the RST pin is driven low, when a Watchdog reset occurs or the RESET instruction is executed. This signal may be used to inform other devices in a system that the XA-S3 has been reset.
2000 Dec 01
31
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
RSTSRC Address:463h Not bit Addressable Reset Value: see below BIT RSTSRC.7 RSTSRC.6 RSTSRC.5 RSTSRC.4 RSTSRC.3 RSTSRC.2 RSTSRC.1 RSTSRC.0 SYMBOL -- -- -- -- -- R_WD R_CMD R_EXT
MSB -- -- -- -- -- R_WD
LSB R_CMD R_EXT
FUNCTION Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Reserved for future use. Should not be set to 1 by user programs. Indicates that the last reset was caused by a watchdog timer overflow. Indicates that the last reset was caused by execution of the RESET instruction. Indicates that the last reset was caused by the external RST input.
SU00942
Figure 24. Reset source register (RSTSRC)
INTERRUPTS
XA-S3 interrupt sources include the following:
* External interrupts 0 and 1 (2) * Timer 0, 1, and 2 interrupts (3) * PCA: 1 global and 5 channel interrupts (6) * A/D interrupt (1) * UART 0 transmitter and receiver interrupts (2) * UART 1 transmitter and receiver interrupts (2) * I2C interrupt (1) * Software interrupts (7)
There are a total of 17 hardware interrupt sources, enable bits, priority bit sets, etc. The XA-S3 supports a total of 17 maskable event interrupt sources (for the various XA peripherals), seven software interrupts, 5
exception interrupts (plus reset), and 16 traps. The maskable event interrupts share a global interrupt disable bit (the EA bit in the IEL register) and each also has a separate individual interrupt enable bit (in the IEL or IEH registers). Only three bits of the IPA register values are used on the XA-S3. Each event interrupt can be set to occur at one of 8 priority levels via bits in the Interrupt Priority (IP) registers, IPA0 through IPA5. The value 0 in the IPA field gives the interrupt priority 0, in effect disabling the interrupt. A value of 1 gives the interrupt a priority of 9, the value 2 gives priority 10, etc. The result is the same as if all four bits were used and the top bit set for all values except 0. Details of the priority scheme may be found in the XA User Guide. The complete interrupt vector list for the XA-S3, including all 4 interrupt types, is shown in the following tables. The tables include the address of the vector for each interrupt, the related priority register bits (if any), and the arbitration ranking for that interrupt source. The arbitration ranking determines the order in which interrupts are processed if more than one interrupt of the same priority occurs simultaneously.
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION Reset (h/w, watchdog, s/w) Breakpoint Trace Stack Overflow Divide by 0 User RETI TRAP 0-15 (software) VECTOR ADDRESS 0000-0003 0004-0007 0008-000B 000C-000F 0010-0013 0014-0017 0040-007F ARBITRATION RANKING 0 (High) 1 1 1 1 1 1
2000 Dec 01
32
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
EVENT INTERRUPTS
DESCRIPTION External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Timer 2 Interrupt PCA Interrupt A/D Interrupt Serial Port 0 Rx Serial Port 0 Tx Serial Port 1 Rx Serial Port 1 Tx PCA channel 0 PCA channel 1 PCA channel 2 PCA channel 3 PCA channel 4 I2C Interrupt FLAG BIT IE0 TF0 IE1 TF1 TF2 (EXF2) CCF0-CCF4, CF ADINT RI_0 TI_0 RI_1 TI_1 CCF0 CCF1 CCF2 CCF3 CCF4 SI VECTOR ADDRESS 0080-0083 0084-0087 0088-008B 008C-008F 0090-0093 0094-0097 0098-009B 00A0-00A3 00A4-00A7 00A8-00AB 00AC-00AF 00C0-00C3 00C4-00C7 00C8-00CB 00CC-00CF 00D0-00D3 00D4-00D7 ENABLE BIT EX0 ET0 EX1 ET1 ET2 EPC EAD ERI0 ETI0 ERI1 ETI1 EC0 EC1 EC2 EC3 EC4 EI2 INTERRUPT PRIORITY IPA0.2-0 (PX0) IPA0.6-4 (PT0) IPA1.2-0 (PX1) IPA1.6-4 (PT1) IPA2.2-0 (PT2) IPA2.6-4 (PPC) IPA3.2-0 (PAD) IPA4.2-0 (PRI0) IPA4.6-4 (PTI0) IPA5.2-0 (PRI1) IPA5.6-4 (PTI1) IPB0.2-0 (PC0) IPB0.6-4 (PC1) IPB1.2-0 (PC2) IPB1.6-4 (PC3) IPB2.2-0 (PC4) IPB2.6-4 (PI2) ARBITRATION RANKING 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 21 22
SOFTWARE INTERRUPTS
DESCRIPTION Software Interrupt 1 Software Interrupt 2 Software Interrupt 3 Software Interrupt 4 Software Interrupt 5 Software Interrupt 6 Software Interrupt 7 FLAG BIT SWR1 SWR2 SWR3 SWR4 SWR5 SWR6 SWR7 VECTOR ADDRESS 0100-0103 0104-0107 0108-010B 010C-010F 0110-0113 0114-0117 0118-011B ENABLE BIT SWE1 SWE2 SWE3 SWE4 SWE5 SWE6 SWE7 INTERRUPT PRIORITY (fixed at 1) (fixed at 2) (fixed at 3) (fixed at 4) (fixed at 5) (fixed at 6) (fixed at 7)
2000 Dec 01
33
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
ABSOLUTE MAXIMUM RATINGS
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer, not device power consumption) RATING -55 to +125 -65 to +150 0 to +13.0 -0.5 to VDD+0.5 V 15 1.5 UNIT C C V V mA W
DC ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, unless otherwise specified. Tamb = 0 to +70C for commercial, Tamb = -40C to +85C for industrial, unless otherwise specified. LIMITS SYMBOL IDD IID IPD PARAMETER Power supply current, operating Power supply current, Idle mode Power supply current, Power Down mode TEST CONDITIONS 5.0 V, 30 MHz 5.0 V, 30 MHz 5.0 V, 3.0 V 5.0 V, 3.0 V, -40 to +85C VRAM VIL VIH RAM keep-alive voltage Input low voltage Input high voltage, except XTAL1, RST VDD = 5.0 V VDD = 3.0 V VIH1 VOL Input high voltage to XTAL1, RST Output low voltage, all ports, ALE, PSEN4, CLKOUT For both 3.0 V and 5.0 V IOL = 3.2 mA, VDD = 5.0 V IOL = 1.0 mA, VDD = 3.0 V VOH1 Output high voltage, all ports, ALE, PSEN2, CLKOUT IOH = -100 A, VDD = 4.5 V IOH = -30 A, VDD = 2.7 V VOH2 Output high voltage, all ports ALE, PSEN3, CLKOUT IOH = -3.2 mA, VDD = 4.5 V IOH = -1.0 mA, VDD = 2.7 V CIO IIL ILI ITL Input/Output pin capacitance1 VIN = 0.45 V VIN = VIL or VIH At VDD = 5.5 V At VDD = 2.7 V Logical 0 input current, all ports7 Input leakage current, all ports6 Logical 1 to 0 transition current, all ports5 2.4 2.0 2.4 2.2 15 -50 10 -650 -250 1.5 -0.5 2.2 2.0 0.7 VDD 0.5 0.4 0.22 VDD 5 MIN TYP MAX 80 35 100 150 UNIT mA mA A A V V V V V V V V V V V pF A A A A
NOTES: 1. Maximum 15pF for EA/VPP. 2. Ports in quasi-bidirectional mode with weak pullup (applies to ALE, PSEN only during RESET). 3. Ports in PUSH-PULL mode, both pullup and pulldown assumed to be the same strength. 4. In all output modes. 5. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when VIN is approximately 2 V. 6. Measured with port in high impedance mode. 7. Measured with port in quasi-bidirectional mode. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15 mA Maximum IOL per port pin: Maximum IOL per 8-bit port: 26 mA 71 mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
2000 Dec 01
34
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
8-BIT MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70C for commercial, Tamb = -40 to +85C for industrial, unless otherwise specified. LIMITS SYMBOL AVDD AIDD AIID AIPD PARAMETER Analog supply voltage Analog supply current (operating) Analog supply current (Idle mode) Analog supply current (Power-Down mode) Commercial temperature range Industrial temperature range AVIN RREF CIA DLe ILe OSe Ge Ae MCTC Ct Analog input voltage Resistance between VREF+ and VREF- Analog input capacitance Differential non-linearity1, 2, 3 Integral non-linearity1, 4 Offset error1, 5 error1, 7 port8 Gain error1, 6 Absolute voltage AVSS -0.2 125 Port 5 = 0 to AVDD TEST CONDITIONS MIN 2.7 MAX 3.3 2.5 2.5 100 150 AVDD +0.2 225 15 1 1 2.5 1 3 1 0 - 100 kHz -60 UNIT V mA A A A V k pF LSB LSB LSB % LSB LSB dB
Channel-to-channel matching Crosstalk between inputs of
NOTES: 1. Conditions: AVREF- = 0 V; AVREF+ = 3.07 V. 2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25. 3. The ADC is monotonic, there are no missing codes. 4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25. 5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. See Figure 25. 6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25. 7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design.
2000 Dec 01
35
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
10-BIT10 MODE A/D CONVERTER DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70C for commercial, Tamb = -40 to +85C for industrial, unless otherwise specified. LIMITS SYMBOL AVDD AIDD AIID AIPD PARAMETER Analog supply voltage Analog supply current (operating) Analog supply current (Idle mode) Analog supply current (Power-Down mode) Commercial temperature range Industrial temperature range AVIN RREF CIA DLe ILe OSe Ge Ae MCTC Ct Analog input voltage Resistance between VREF+ and VREF- Analog input capacitance Differential non-linearity1, 2, 3 Integral non-linearity1, 4 Offset error1, 5 averaging)1, 7 port8 Gain error1, 6 Absolute voltage error (with AVSS -0.2 125 Port 5 = 0 to AVDD TEST CONDITIONS MIN 2.7 MAX 3.3 2.5 2.5 100 150 AVDD +0.2 225 15 1 9 2.5 9 6 8
9
UNIT V mA A A A V k pF LSB LSB LSB % LSB LSB dB
1 9
9
Channel-to-channel matching Crosstalk between inputs of 0 - 100 kHz
1 -60
NOTES: 1. Conditions: AVREF- = 0 V; AVREF+ = 3.07 V. 2. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. See Figure 25. 3. The ADC is monotonic, there are no missing codes. 4. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 25. 5. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and the straight line which fits the ideal transfer curve. See Figure 25. 6. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. See Figure 25. 7. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 8. This should be considered when both analog and digital signals are input simultaneously to Port 5. Parameter is guaranteed by design. 9. 10-bit mode only. 10. 10-bit mode is only operational up to fC = 20 MHz.
2000 Dec 01
36
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
Offset error OSe 255 Full Scale error FSe
Gain error Ge
254
253
252
251
250 (2)
7 Code Out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal)
0 1 2 3 4 5 6 7 250 251 252 253 254 255 256
AVIN (LSBideal) Offset error OSe 1 LSB = (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve.
AVREF+
- AVREF-
256
SU01010
Figure 25. ADC Conversion Characteristic
2000 Dec 01
37
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
AC ELECTRICAL CHARACTERISTICS (5 V)
VDD = 4.5 V to 5.5 V; Tamb = 0 to +70C for commercial, Tamb = -40C to +85C for industrial. SYMBOL FIGURE PARAMETER LIMITS MIN 0 1/fC tC * 0.5 tC * 0.4 5 5 (V1 * tC) - 6 (V1 * tC) - 12 (tC/2) - 10 (V2 * tC) - 10 (tC/2) - 7 (V3 * tC) - 36 (V4 * tC) - 29 (V2 * tC) - 29 0 tC - 8 0 (V7 * tC) - 10 (tC/2) - 7 (V6 * tC) - 36 (V5 * tC) - 29 (V7 * tC) - 29 0 tC - 8 0 (V8 * tC) - 10 (V12 * tC) - 10 (V13 * tC) - 22 (V11 * tC) - 5 (V9 * tC) - 22 (V11 * tC) - 7 (V10 * tC) - 30 (V10 * tC) - 5 MAX 30 UNIT
External Clock fC tC tCHCX tCLCX tCLCH tCHCL Address Cycle tLHLL tAVLL tLLAX tPLPH tLLPL tAVIVA tAVIVB tPLIV tPHIX tPHIZ tIXUA tRLRH tLLRL tAVDVA tAVDVB tRLDV tRHDX tRHDZ tDXUA tWLWH tLLWL tQVWX tWHQX tAVWL tUAWH Wait Input tWTH tWTL 31 31 WAIT stable after bus strobe (RD, WR, or PSEN) asserted WAIT hold after bus strobe (RD, WR, or PSEN) asserted ns ns 26, 28, 30 26, 28, 30 26, 28, 30 26 26 26 27 26 26 26 26 28 28 28 29 28 28 28 28 30 30 30 30 30 30 ALE pulse width (programmable) Address valid to ALE de-asserted (set-up) Address hold after ALE de-asserted PSEN pulse width ALE de-asserted to PSEN asserted Address valid to instruction valid, ALE cycle (access time) Address valid to instruction valid, non-ALE cycle (access time) PSEN asserted to instruction valid (enable time) Instruction hold after PSEN de-asserted Bus 3-State after PSEN de-asserted Hold time of unlatched part of address after instruction latched RD pulse width ALE de-asserted to RD asserted Address valid to data input valid, ALE cycle (access time) Address valid to data input valid, non-ALE cycle (access time) RD low to valid data in (enable time) Data hold time after RD de-asserted Bus 3-State after RD de-asserted (disable time) Hold time of unlatched part of address after data latched WR pulse width ALE falling edge to WR asserted Data valid before WR asserted (data set-up time) Data hold time after WR de-asserted (Note 6) Address valid to WR asserted (address set-up time) (Note 5) Hold time of unlatched part of address after WR is de-asserted ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 32 32 32 32 32 Oscillator frequency Clock period and CPU timing cycle Clock high-time (Note 7) Clock low time (Note 7) Clock rise time (Note 7) Clock fall time (Note 7) MHz ns ns ns ns ns
Code Read Cycle
Data Read Cycle
Data Write Cycle
NOTES ON PAGE 41.
2000 Dec 01
38
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output. SYMBOL FIGURE PARAMETER LIMITS MIN - - - 2 - - 20 0 - - - 20 0 - - - 4 0 21 MAX 13 9 18 - 14 12 - - tC-8 12 10 - - tC-8 12 10 - - 4 UNIT
Address Cycle tCHLH tCLLL tCHAV tCHAX tCHPL tCHPH tIVCH tCHIX tCHIZ tCHRL tCHRH tDVCH tCHDX tCHDZ tCHWL tCHWH tQVCH tCHQX Wait Input tCHWTH 31 WAIT valid prior to CLKOUT rising edge8 ns NOTES ON PAGE 41. 26 26 26 26 26 26 26 26 26 28 28 28 28 28 30 30 30 30 CLKOUT rising edge to ALE rising edge CLKOUT falling edge to ALE falling edge CLKOUT rising edge to address valid CLKOUT rising edge to address changing (hold time) CLKOUT rising edge to PSEN asserted CLKOUT rising edge to PSEN de-asserted Instruction valid to CLKOUT rising edge (setup time) CLKOUT rising edge to instruction changing (hold time) CLKOUT rising edge to Bus 3-State (code read) CLKOUT rising edge to RD asserted CLKOUT rising edge to RD de-asserted Data valid to CLKOUT rising edge (setup time) CLKOUT rising edge to Data changing (hold time) CLKOUT rising edge to Bus 3-State (data read) CLKOUT falling edge to WR asserted CLKOUT rising edge to WR de-asserted Data valid to CLKOUT rising edge (setup time) CLKOUT rising edge to Data changing (hold time) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Code Read Cycle
Data Read Cycle
Data Write Cycle
2000 Dec 01
39
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
AC ELECTRICAL CHARACTERISTICS (3 V)
VDD = 2.7 V to 4.5 V; Tamb = 0 to +70C for commercial, Tamb = -40C to +85C for industrial. SYMBOL FIGURE PARAMETER LIMITS MIN (V1 * tC) - 10 (V1 * tC) - 18 (tC/2) - 12 (V2 * tC) - 12 (tC/2) - 9 (V3 * tC) - 58 (V4 * tC) - 52 (V2 * tC) - 52 0 tC - 8 0 (V7 * tC) - 12 (tC/2) - 9 (V6 * tC) - 58 (V5 * tC) - 52 (V7 * tC) - 52 0 tC - 8 0 (V8 * tC) - 12 (V12 * tC) - 10 (V13 * tC) - 28 (V11 * tC) - 8 (V9 * tC) - 28 (V11 * tC) - 10 (V10 * tC) - 40 (V10 * tC) - 5 MAX UNIT
Address Cycle tLHLL tAVLL tLLAX tPLPH tLLPL tAVIVA tAVIVB tPLIV tPHIX tPHIZ tIXUA tRLRH tLLRL tAVDVA tAVDVB tRLDV tRHDX tRHDZ tDXUA tWLWH tLLWL tQVWX tWHQX tAVWL tUAWH Wait Input tWTH tWTL 31 31 WAIT stable after bus strobe (RD, WR, or PSEN) asserted WAIT hold after bus strobe (RD, WR, or PSEN) asserted ns ns 26, 28, 30 26, 28, 30 26, 28, 30 26 26 26 27 26 26 26 26 28 28 28 29 28 28 28 28 30 30 30 30 30 30 ALE pulse width (programmable) Address valid to ALE de-asserted (set-up) Address hold after ALE de-asserted PSEN pulse width ALE de-asserted to PSEN asserted Address valid to instruction valid, ALE cycle (access time) Address valid to instruction valid, non-ALE cycle (access time) PSEN asserted to instruction valid (enable time) Instruction hold after PSEN de-asserted Bus 3-State after PSEN de-asserted Hold time of unlatched part of address after instruction latched RD pulse width ALE de-asserted to RD asserted Address valid to data input valid, ALE cycle (access time) Address valid to data input valid, non-ALE cycle (access time) RD low to valid data in (enable time) Data hold time after RD de-asserted Bus 3-State after RD de-asserted (disable time) Hold time of unlatched part of address after data latched WR pulse width ALE falling edge to WR asserted Data valid before WR asserted (data set-up time) Data hold time after WR de-asserted (Note 6) Address valid to WR asserted (address set-up time) (Note 5) Hold time of unlatched part of address after WR is de-asserted ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Code Read Cycle
Data Read Cycle
Data Write Cycle
NOTES ON PAGE 41.
2000 Dec 01
40
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output. SYMBOL FIGURE PARAMETER LIMITS MIN - - - 2 - - 30 0 - - - 28 0 - - - 4 0 30 MAX 15 11 29 - 16 15 - - tC-8 20 16 - - tC-8 19 16 - - 4 UNIT
Address Cycle tCHLH tCLLL tCHAV tCHAX tCHPL tCHPH tIVCH tCHIX tCHIZ tCHRL tCHRH tDVCH tCHDX tCHDZ tCHWL tCHWH tQVCH tCHQX Wait Input tCHWTH 31 WAIT valid prior to CLKOUT rising edge8 ns NOTES: 1. Load capacitance for all outputs = 50 pF. 2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to the XA User Guide for details of the bus timing settings. V1) This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1. V2) This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and ALEW bits in the BTRL register. - For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of determining peripheral timing requirements. - For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2. Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 - (1.5 + 0.5) = 2. V3) This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if CRA1/0 = 11). V4) This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. V5) This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. V6) This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11). 26 26 26 26 26 26 26 26 26 28 28 28 28 28 30 30 30 30 CLKOUT rising edge to ALE rising edge CLKOUT falling edge to ALE falling edge CLKOUT rising edge to address valid CLKOUT rising edge to address changing (hold time) CLKOUT rising edge to PSEN asserted CLKOUT rising edge to PSEN de-asserted Instruction valid to CLKOUT rising edge (setup time) CLKOUT rising edge to instruction changing (hold time) CLKOUT rising edge to Bus 3-State (code read) CLKOUT rising edge to RD asserted CLKOUT rising edge to RD de-asserted Data valid to CLKOUT rising edge (setup time) CLKOUT rising edge to Data changing (hold time) CLKOUT rising edge to Bus 3-State (data read) CLKOUT falling edge to WR asserted CLKOUT rising edge to WR de-asserted Data valid to CLKOUT rising edge (setup time) CLKOUT rising edge to Data changing (hold time) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Code Read Cycle
Data Read Cycle
Data Write Cycle
2000 Dec 01
41
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
This variable represents the programmed width of the RD pulse as determined by the DR1 and DR0 bits or the DRA1, DRA0 in the BTRH register, and the SLEW bit in the BTRL register. Note that during a 16-bit operation on an 8-bit external bus, RD remains low and does not exhibit a transition between the first and second byte bus cycles. V7 still applies for the purpose of determining peripheral timing requirements. The timing for the first byte is for a bus cycle with ALE, the timing for the second byte is for a bus cycle with no ALE. - For a bus cycle with no ALE, V7 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11. - For a bus cycle with an ALE, V7 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and 5 if DRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5). Example: if DRA1/0 = 00 and ALEW = 0, then V7 = 2 - (0.5 +0.5) = 1. V8) This variable represents the programmed width of the WRL and/or WRH pulse as determined by the WM1 bit in the BTRL register. V8 = 1 if WM1 = 0, and 2 if WM1 = 1. V9) This variable represents the programmed address setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the value of V8. - For a bus cycle with an ALE, V9 = the total bus write cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8) minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DWA1/0 = 10, WM0 = 1, and WM1 = 1, then V9 = 4 - 1 - 2 = 1. - For a bus cycle with no ALE, V9 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WMo = 0 and 1 if WM0 = 1). Example: If DW1/0 = 11, WM0 = 1, and WM1 = 0, then V9 = 5 - 1 - 1 = 3. V10) This variable represents the length of a bus strobe for calculation of WAIT set-up and hold times. The strobe may be RD (for data read cycles), WRL and/or WRH (for data write cycles), or PSEN (for code read cycles), depending on the type of bus cycle being widened by WAIT. V10 = 2 for WAIT associated with a code read cycle using PSEN. V10 = V8 for a data write cycle using WRL and/or WRH. V10 = V7 - 1 for a data read cycle using RD. This means that a single clock data read cycle cannot be stretched using WAIT. If WAIT is used to vary the duration of data read cycles, the RD strobe width must be set to be at least two clocks in duration. Also see Note 4. V11) This variable represents the programmed write hold time as determined by the WM0 bit in the BTRL register. V11 0 if the WM0 bit = 0, and 1 if the WM0 bit = 1. V12) this variable represents the programmed period between the end of the ALE pulse and the beginning of the WRL and/or WRH pulse as determined by the data write cycle duration (defined by the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. V12 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the width of the ALE pulse (V1). Example: If SWA1/0 = 11, WM0 = 1, WM1 = 0, and ALEW = 1, then V12 = 5 - 1 - 1 - 1.5 = 1.5. V13) This variable represents the programmed data setup time for a write as determined by the data write cycle duration (defined by DW1 and DW0 or the DWA1 and DWA0 bits in the BTRH register), the WM0 bit in the BTRL register, and the values of V1 and V8. - For a bus cycle with an ALE, V13 = the total bus cycle duration (2 if DWA1/0 = 00, 3 if DWA1/0 = 01, 4 if DWA1/0 = 10, and 5 if DWA1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1), minus the number of clocks used by ALE (V1 + 0.5). Example: If DWA1/0 = 11, WM0 = 1, WM1 = 1, and ALEW = 0, then V13 = 5 - 1 - 2 - 1 = 1. - For a bus cycle with no ALE, V13 = the total bus cycle duration (2 if DW1/0 = 00, 3 if DW1/0 = 01, 4 if DW1/0 = 10, and 5 if DW1/0 = 11) minus the number of clocks used by the WRL and/or WRH pulse (V8), minus the number of clocks used by data hold time (0 if WM0 = 0 and 1 if WM0 = 1). Example: If DW1/0 = 01, WM0 = 1, and WM1 = 0, then V13 = 3 - 1 - 1 = 1. 3. Not all combinations of bus timing configuration values result in valid bus cycles. Please refer to the XA User Guide section on the External Bus for details. 4. When code is being fetched for execution on the external bus, a burst mode fetch is used that dows not have PSEN edges in every fetch cycle. This would be A3-A0 for an 8-bit bus, and A3-A1 for a 16-bit bus. Also, a 16-bit read operation conducted on an 8-bit wide bus similarly does not include two separate RD strobes. So, a rising edge on the low order address line (A0) must be used to trigger a WAIT in the second half of such a cycle. 5. This parameter is provided for peripherals that have the data clocked in on the falling edge of the WR strobe. This is not usually the case and in most applications this parameter is not used. 6. Please note that the XA-S3 requires that extended data bus hold time (WM0 = 1) to be used with external bus write cycles. 7. Applies only to an external clock source, not when a crystal is connected to the XTAL1 and XTAL2 pins. 8. WAIT should not change between these times. V7)
2000 Dec 01
42
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
AC WAVEFORMS
CLKOUT tCHLH tCLLL tLHLL ALE tCHAV tCHAX tLLPL PSEN tIVCH tAVLL Multiplexed Address and Data tLLAX tPLIV tCHIX tPHIX INSTR IN* tAVIVA Unmultiplexed Address A0 or A1-A3, A12-A23 tIXUA tPLPH tPHIZ tCHIZ tCHPL tCHPH
A4-A11 or A4-A23
*INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits). Figure 26. External Program Memory Read Cycle (ALE Cycle)
SU00943A
PSEN
Multiplexed Address and Data tAVIVB Unmultiplexed Address A0 or A1-A3, A12-A23
INSTR IN*
*INSTR IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits). Figure 27. External Program Memory Read Cycle (Non-ALE Cycle)
SU00949
2000 Dec 01
43
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CLKOUT tCHRL tLHLL ALE tRLRH tLLRL RD tDVCH tAVLL Multiplexed Address and Data tLLAX tRLDV tCHDX tRHDX DATA IN* tAVDVA Unmultiplexed Address A0 or A1-A3, A12-A23 tDXUA tRHDZ tCHDZ tCHRH
A4-A11 or A4-A23
*DATA IN is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits). Figure 28. External Data Memory Read Cycle (ALE Cycle)
SU00944
RD
Multiplexed Address and Data tAVDVB Unmultiplexed Address A0-A3, A12-A23
D0-D7
SU00950A
Figure 29. External Data Memory Read Cycle (Non-ALE Cycle)
2000 Dec 01
44
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
CLKOUT tCHWL tCHWH tCHQZ ALE tCHQX tWHQX
tLLWL WR
tWLWH
tAVLL Multiplexed Address and Data
tLLAX
tQVWX
tQVCH
A4-A11 or A4-A23 tAVWL
DATA OUT* tUAWH A0 or A1-A3, A12-A23
Unmultiplexed Address
*DATA OUT is either D0-D7 or D0-D15, depending on the bus width (8 or 16 bits). Figure 30. External Data Memory Write Cycle
SU00945
XTAL1 tCRAR ALE
ADDRESS BUS
WAIT tCHWTH BUS STROBE (WRL, WRH, RD, OR PSEN) tWTH tWTL tCHWTL
(The dashed line shows the strobe without WAIT.)
SU01068
Figure 31. WAIT Signal Timing
2000 Dec 01
45
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
VDD-0.5 0.45V
0.7VDD 0.2VDD-0.1
tCHCL
tCLCX tC
tCHCX tCLCH
SU00842
Figure 32. External Clock Drive
VDD-0.5 0.2VDD+0.9 0.2VDD-0.1 0.45V NOTE: AC inputs during testing are driven at VDD -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at the 50% point of transitions.
SU00703A
Figure 33. AC Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00011
Figure 34. Float Waveform
VDD
VDD
VDD RST VDD
VDD
RST EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS EA
SU00591B
SU00590B
Figure 35. IDD Test Condition, Active Mode All other pins are disconnected
Figure 36. IDD Test Condition, Idle Mode All other pins are disconnected
2000 Dec 01
46
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
90 80 70 60 mA 50 40 Max. IDD (Idle) 30 Typical IDD (Idle) 20 10 0 0 5 10 15 Frequency (MHz) Figure 37. IDD vs. Frequency Valid only within frequency specification of the device under test. 20 25 30
SU01228
Max. IDD (Active)
Typical IDD (Active)
VDD-0.5 0.45V
0.7VDD 0.2VDD-0.1
tCHCL
tCLCX tCL
tCHCX tCLCH
SU00608A
Figure 38. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5 ns
VDD VDD
VDD RST
EA (NC) XTAL2 XTAL1 VSS
SU00585A
Figure 39. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD=2 V to 5.5 V
2000 Dec 01
47
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
EPROM CHARACTERISTICS
The XA-S3 is programmed by using a modified Improved Quick-Pulse ProgrammingTM algorithm. This algorithm is essentially the same as that used by 80C51 family EPROM parts. However different pins are used for many programming functions. The XA-S3 contains three signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an XA-S3 manufactured by Philips.
Security Bits
With none of the security bits programmed the code in the program memory can be verified. When only security bit 1 is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory. All further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. (See Table 6.)
Table 6. Program Security Bits
PROGRAM LOCK BITS SB1 1 2 3 4 U P P P SB2 U U P P SB3 U U U P PROTECTION DESCRIPTION No Program Security features enabled. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
ROM CODE SUBMISSION
When submitting ROM code for the XA-S3, the following must be specified: 1. 32k byte user ROM data 2. ROM security bits. ADDRESS 0000H to 7FFFH 8020H 8020H CONTENT DATA SEC SEC BIT(S) 7:0 0 1 COMMENT User ROM Data ROM Security Bit 1 ROM Security Bit 2 0 = enable security 1 = disable security ROM Security Bit 3 0 = enable security 1 = disable security
8020H
SEC
3
TMTrademark phrase of Intel Corporation. 2000 Dec 01 48
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
2000 Dec 01
49
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SOT315-1
2000 Dec 01
50
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
NOTES
2000 Dec 01
51
Philips Semiconductors
Preliminary specification
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V-5.5 V), I2C, 2 UARTs, 16 MB address range
XA-S3
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 12-00 Document order number: 9397 750 07816
Philips Semiconductors
2000 Dec 01 52

▲Up To Search▲

Price & Availability of PXAS30KFA

	To Download PXAS30KFA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .